Japanese Patent Laid-Open No. 11-306762 (hereinafter referred to as “Document”) discloses, as shown in FIG. 23, an SRAM memory array in which each bit line BL/BLB is provided with a column sense amplifier CSA to be connected to a global bit line GBL/GBLB. In this structure, the column sense amplifier can be selectively activated by a sense amplifier activating signal S for each block and a Y address signal YB, so that power consumption can be reduced.
Prior to the present invention, the inventors of the present invention have studied a control method used in the case where a potential of a bit line of DRAM is detected by a differential, gate-receiving amplifier, i.e., by a so-called direct sense amplifier. They have noticed the following points to be considered when the amplifier control method in the above-mentioned Document is used for the direct sense amplifier of DRAM. Firstly, since large-sized MOS transistors MN 20 and MN 21 are directly connected to a global bit line (corresponding to a local IO line to be connected to an output of the direct sense amplifier in DRAM), a load capacity of the global bit line (local IO line) is increased. In the DRAM, a number of direct sense amplifiers, e.g., approximately 32 to 128 direct sense amplifiers are normally connected to the local IO line. Also, since the local IO line and a main IO line lying ahead have long distances and large loads and the gates of the MOS transistors serving as a differential pair are long in order to reduce a threshold voltage offset, the gate width of the MN 20 and MN 21 is required to be, for example, 4 μm or longer. Therefore, like the CSA as shown in FIG. 23, in the structure where all differential pairs of a non-selected direct sense amplifier are visible, the load capacity of the local IO line is heavy, so that an operation with a high speed is difficult.
Secondly, the bit-line pre-charge level of DRAM is half of a level VDL of a power-supply voltage or a level VDL obtained by lowering the power-supply voltage, that is, VDL/2. Therefore, when a negative signal occurs on the BL and the level of the BL is decreased to a level lower than VDL/2, the MN 21 is cut off and the channel capacitance of MN 21 is made invisible from the local IO line. However, when a positive signal occurs on the BL and the level of the BL is increased to a level higher than VDL/2, the MN 21 is conducted and the channel capacity is made visible. Therefore, the capacity of the local IO line is significantly changed depending on a data pattern on the bit line. That is, a operational speed is significantly changed depending on a operation condition, so that there is the problem that a post-manufacturing test is made complicated.
Therefore, a first object to be solved by the present invention is to have a configuration in which a direct sense amplifier in a random access memory such as DRAM or SRAM can be selectively activated, wherein the load capacity of a local IO line is reduced and also its data pattern dependency is reduced. Also, a second problem to be solved by the present invention is to reduce noise in the direct sense amplifier in performing an operation at a high speed and to increase an operation margin. Furthermore, a third problem in the present invention is to double the number of bits to be read from a single memory array without increasing chip size.
The above and other objects and effects in the present invention will be apparent from the description of this specification and the accompanying drawings.